3312af6e07
We currently use an old version of libgcrypt which results in us having fewer ciphers and missing on many other improvements. Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com>
465 lines
14 KiB
ArmAsm
465 lines
14 KiB
ArmAsm
/* sha512-arm.S - ARM assembly implementation of SHA-512 transform
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*
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* Copyright (C) 2016 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*
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* This file is part of Libgcrypt.
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*
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* Libgcrypt is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as
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* published by the Free Software Foundation; either version 2.1 of
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* the License, or (at your option) any later version.
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*
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* Libgcrypt is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <config.h>
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#if defined(__ARMEL__)
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#ifdef HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS
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.text
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.syntax unified
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.arm
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/* structure of SHA512_CONTEXT */
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#define hd_a 0
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#define hd_b ((hd_a) + 8)
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#define hd_c ((hd_b) + 8)
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#define hd_d ((hd_c) + 8)
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#define hd_e ((hd_d) + 8)
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#define hd_f ((hd_e) + 8)
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#define hd_g ((hd_f) + 8)
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#define hd_h ((hd_g) + 8)
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/* register macros */
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#define RK r2
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#define RElo r0
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#define REhi r1
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#define RT1lo r3
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#define RT1hi r4
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#define RT2lo r5
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#define RT2hi r6
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#define RWlo r7
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#define RWhi r8
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#define RT3lo r9
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#define RT3hi r10
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#define RT4lo r11
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#define RT4hi ip
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#define RRND lr
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/* variable offsets in stack */
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#define ctx (0)
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#define data ((ctx) + 4)
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#define nblks ((data) + 4)
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#define _a ((nblks) + 4)
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#define _b ((_a) + 8)
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#define _c ((_b) + 8)
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#define _d ((_c) + 8)
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#define _e ((_d) + 8)
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#define _f ((_e) + 8)
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#define _g ((_f) + 8)
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#define _h ((_g) + 8)
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#define w(i) ((_h) + 8 + ((i) % 16) * 8)
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#define STACK_MAX (w(15) + 8)
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/* helper macros */
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#define ldr_unaligned_be(rout, rsrc, offs, rtmp) \
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ldrb rout, [rsrc, #((offs) + 3)]; \
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ldrb rtmp, [rsrc, #((offs) + 2)]; \
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orr rout, rout, rtmp, lsl #8; \
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ldrb rtmp, [rsrc, #((offs) + 1)]; \
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orr rout, rout, rtmp, lsl #16; \
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ldrb rtmp, [rsrc, #((offs) + 0)]; \
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orr rout, rout, rtmp, lsl #24;
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#ifdef __ARMEL__
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/* bswap on little-endian */
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#ifdef HAVE_ARM_ARCH_V6
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#define be_to_host(reg, rtmp) \
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rev reg, reg;
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#else
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#define be_to_host(reg, rtmp) \
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eor rtmp, reg, reg, ror #16; \
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mov rtmp, rtmp, lsr #8; \
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bic rtmp, rtmp, #65280; \
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eor reg, rtmp, reg, ror #8;
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#endif
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#else
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/* nop on big-endian */
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#define be_to_host(reg, rtmp) /*_*/
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#endif
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#define host_to_host(x, y) /*_*/
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#define read_u64_aligned_4(rin, offs, lo0, hi0, lo1, hi1, lo2, hi2, lo3, hi3, convert, rtmp) \
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ldr lo0, [rin, #((offs) + 0 * 8 + 4)]; \
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ldr hi0, [rin, #((offs) + 0 * 8 + 0)]; \
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ldr lo1, [rin, #((offs) + 1 * 8 + 4)]; \
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ldr hi1, [rin, #((offs) + 1 * 8 + 0)]; \
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ldr lo2, [rin, #((offs) + 2 * 8 + 4)]; \
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convert(lo0, rtmp); \
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ldr hi2, [rin, #((offs) + 2 * 8 + 0)]; \
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convert(hi0, rtmp); \
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ldr lo3, [rin, #((offs) + 3 * 8 + 4)]; \
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convert(lo1, rtmp); \
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ldr hi3, [rin, #((offs) + 3 * 8 + 0)]; \
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convert(hi1, rtmp); \
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convert(lo2, rtmp); \
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convert(hi2, rtmp); \
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convert(lo3, rtmp); \
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convert(hi3, rtmp);
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#define read_be64_aligned_4(rin, offs, lo0, hi0, lo1, hi1, lo2, hi2, lo3, hi3, rtmp0) \
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read_u64_aligned_4(rin, offs, lo0, hi0, lo1, hi1, lo2, hi2, lo3, hi3, be_to_host, rtmp0)
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/* need to handle unaligned reads by byte reads */
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#define read_be64_unaligned_4(rin, offs, lo0, hi0, lo1, hi1, lo2, hi2, lo3, hi3, rtmp0) \
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ldr_unaligned_be(lo0, rin, (offs) + 0 * 8 + 4, rtmp0); \
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ldr_unaligned_be(hi0, rin, (offs) + 0 * 8 + 0, rtmp0); \
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ldr_unaligned_be(lo1, rin, (offs) + 1 * 8 + 4, rtmp0); \
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ldr_unaligned_be(hi1, rin, (offs) + 1 * 8 + 0, rtmp0); \
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ldr_unaligned_be(lo2, rin, (offs) + 2 * 8 + 4, rtmp0); \
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ldr_unaligned_be(hi2, rin, (offs) + 2 * 8 + 0, rtmp0); \
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ldr_unaligned_be(lo3, rin, (offs) + 3 * 8 + 4, rtmp0); \
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ldr_unaligned_be(hi3, rin, (offs) + 3 * 8 + 0, rtmp0);
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/***********************************************************************
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* ARM assembly implementation of sha512 transform
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***********************************************************************/
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/* Round function */
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#define R(_a,_b,_c,_d,_e,_f,_g,_h,W,wi) \
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/* Message expansion, t1 = _h + w[i] */ \
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W(_a,_h,wi); \
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\
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/* w = Sum1(_e) */ \
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mov RWlo, RElo, lsr#14; \
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ldm RK!, {RT2lo-RT2hi}; \
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mov RWhi, REhi, lsr#14; \
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eor RWlo, RWlo, RElo, lsr#18; \
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eor RWhi, RWhi, REhi, lsr#18; \
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ldr RT3lo, [sp, #(_f)]; \
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adds RT1lo, RT2lo; /* t1 += K */ \
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ldr RT3hi, [sp, #(_f) + 4]; \
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adc RT1hi, RT2hi; \
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ldr RT4lo, [sp, #(_g)]; \
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eor RWlo, RWlo, RElo, lsl#23; \
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ldr RT4hi, [sp, #(_g) + 4]; \
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eor RWhi, RWhi, REhi, lsl#23; \
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eor RWlo, RWlo, REhi, lsl#18; \
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eor RWhi, RWhi, RElo, lsl#18; \
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eor RWlo, RWlo, REhi, lsl#14; \
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eor RWhi, RWhi, RElo, lsl#14; \
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eor RWlo, RWlo, REhi, lsr#9; \
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eor RWhi, RWhi, RElo, lsr#9; \
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\
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/* Cho(_e,_f,_g) => (_e & _f) ^ (~_e & _g) */ \
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adds RT1lo, RWlo; /* t1 += Sum1(_e) */ \
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and RT3lo, RT3lo, RElo; \
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adc RT1hi, RWhi; \
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and RT3hi, RT3hi, REhi; \
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bic RT4lo, RT4lo, RElo; \
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bic RT4hi, RT4hi, REhi; \
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eor RT3lo, RT3lo, RT4lo; \
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eor RT3hi, RT3hi, RT4hi; \
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\
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/* Load D */ \
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/* t1 += Cho(_e,_f,_g) */ \
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ldr RElo, [sp, #(_d)]; \
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adds RT1lo, RT3lo; \
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ldr REhi, [sp, #(_d) + 4]; \
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adc RT1hi, RT3hi; \
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\
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/* Load A */ \
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ldr RT3lo, [sp, #(_a)]; \
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\
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/* _d += t1 */ \
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adds RElo, RT1lo; \
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ldr RT3hi, [sp, #(_a) + 4]; \
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adc REhi, RT1hi; \
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\
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/* Store D */ \
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str RElo, [sp, #(_d)]; \
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\
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/* t2 = Sum0(_a) */ \
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mov RT2lo, RT3lo, lsr#28; \
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str REhi, [sp, #(_d) + 4]; \
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mov RT2hi, RT3hi, lsr#28; \
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ldr RWlo, [sp, #(_b)]; \
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eor RT2lo, RT2lo, RT3lo, lsl#30; \
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ldr RWhi, [sp, #(_b) + 4]; \
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eor RT2hi, RT2hi, RT3hi, lsl#30; \
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eor RT2lo, RT2lo, RT3lo, lsl#25; \
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eor RT2hi, RT2hi, RT3hi, lsl#25; \
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eor RT2lo, RT2lo, RT3hi, lsl#4; \
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eor RT2hi, RT2hi, RT3lo, lsl#4; \
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eor RT2lo, RT2lo, RT3hi, lsr#2; \
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eor RT2hi, RT2hi, RT3lo, lsr#2; \
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eor RT2lo, RT2lo, RT3hi, lsr#7; \
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eor RT2hi, RT2hi, RT3lo, lsr#7; \
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\
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/* t2 += t1 */ \
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adds RT2lo, RT1lo; \
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ldr RT1lo, [sp, #(_c)]; \
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adc RT2hi, RT1hi; \
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\
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/* Maj(_a,_b,_c) => ((_a & _b) ^ (_c & (_a ^ _b))) */ \
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ldr RT1hi, [sp, #(_c) + 4]; \
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and RT4lo, RWlo, RT3lo; \
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and RT4hi, RWhi, RT3hi; \
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eor RWlo, RWlo, RT3lo; \
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eor RWhi, RWhi, RT3hi; \
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and RWlo, RWlo, RT1lo; \
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and RWhi, RWhi, RT1hi; \
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eor RWlo, RWlo, RT4lo; \
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eor RWhi, RWhi, RT4hi; \
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/* Message expansion */
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#define W_0_63(_a,_h,i) \
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ldr RT3lo, [sp, #(w(i-2))]; \
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adds RT2lo, RWlo; /* _h = t2 + Maj(_a,_b,_c) */ \
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ldr RT3hi, [sp, #(w(i-2)) + 4]; \
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adc RT2hi, RWhi; \
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/* nw = S1(w[i-2]) */ \
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ldr RT1lo, [sp, #(_h)]; /* Load H */ \
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mov RWlo, RT3lo, lsr#19; \
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str RT2lo, [sp, #(_a)]; \
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eor RWlo, RWlo, RT3lo, lsl#3; \
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ldr RT1hi, [sp, #(_h) + 4]; \
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mov RWhi, RT3hi, lsr#19; \
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ldr RT2lo, [sp, #(w(i-7))]; \
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eor RWhi, RWhi, RT3hi, lsl#3; \
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str RT2hi, [sp, #(_a) + 4]; \
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eor RWlo, RWlo, RT3lo, lsr#6; \
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ldr RT2hi, [sp, #(w(i-7)) + 4]; \
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eor RWhi, RWhi, RT3hi, lsr#6; \
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eor RWlo, RWlo, RT3hi, lsl#13; \
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eor RWhi, RWhi, RT3lo, lsl#13; \
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eor RWlo, RWlo, RT3hi, lsr#29; \
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eor RWhi, RWhi, RT3lo, lsr#29; \
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ldr RT3lo, [sp, #(w(i-15))]; \
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eor RWlo, RWlo, RT3hi, lsl#26; \
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ldr RT3hi, [sp, #(w(i-15)) + 4]; \
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\
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adds RT2lo, RWlo; /* nw += w[i-7] */ \
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ldr RWlo, [sp, #(w(i-16))]; \
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adc RT2hi, RWhi; \
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mov RT4lo, RT3lo, lsr#1; /* S0(w[i-15]) */ \
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ldr RWhi, [sp, #(w(i-16)) + 4]; \
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mov RT4hi, RT3hi, lsr#1; \
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adds RT2lo, RWlo; /* nw += w[i-16] */ \
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eor RT4lo, RT4lo, RT3lo, lsr#8; \
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eor RT4hi, RT4hi, RT3hi, lsr#8; \
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eor RT4lo, RT4lo, RT3lo, lsr#7; \
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eor RT4hi, RT4hi, RT3hi, lsr#7; \
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eor RT4lo, RT4lo, RT3hi, lsl#31; \
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eor RT4hi, RT4hi, RT3lo, lsl#31; \
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eor RT4lo, RT4lo, RT3hi, lsl#24; \
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eor RT4hi, RT4hi, RT3lo, lsl#24; \
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eor RT4lo, RT4lo, RT3hi, lsl#25; \
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adc RT2hi, RWhi; \
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\
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/* nw += S0(w[i-15]) */ \
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adds RT2lo, RT4lo; \
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adc RT2hi, RT4hi; \
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\
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/* w[0] = nw */ \
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str RT2lo, [sp, #(w(i))]; \
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adds RT1lo, RWlo; \
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str RT2hi, [sp, #(w(i)) + 4]; \
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adc RT1hi, RWhi;
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#define W_64_79(_a,_h,i) \
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adds RT2lo, RWlo; /* _h = t2 + Maj(_a,_b,_c) */ \
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ldr RWlo, [sp, #(w(i-16))]; \
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adc RT2hi, RWhi; \
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ldr RWhi, [sp, #(w(i-16)) + 4]; \
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ldr RT1lo, [sp, #(_h)]; /* Load H */ \
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ldr RT1hi, [sp, #(_h) + 4]; \
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str RT2lo, [sp, #(_a)]; \
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str RT2hi, [sp, #(_a) + 4]; \
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adds RT1lo, RWlo; \
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adc RT1hi, RWhi;
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.align 3
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.globl _gcry_sha512_transform_arm
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.type _gcry_sha512_transform_arm,%function;
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_gcry_sha512_transform_arm:
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/* Input:
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* r0: SHA512_CONTEXT
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* r1: data
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* r2: u64 k[] constants
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* r3: nblks
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*/
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push {r4-r11, ip, lr};
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sub sp, sp, #STACK_MAX;
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movs RWlo, r3;
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str r0, [sp, #(ctx)];
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beq .Ldone;
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.Loop_blocks:
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str RWlo, [sp, #nblks];
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/* Load context to stack */
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add RWhi, sp, #(_a);
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ldm r0!, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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stm RWhi!, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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ldm r0, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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stm RWhi, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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/* Load input to w[16] */
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/* test if data is unaligned */
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tst r1, #3;
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beq 1f;
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/* unaligned load */
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add RWhi, sp, #(w(0));
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read_be64_unaligned_4(r1, 0 * 8, RT1lo, RT1hi, RT2lo, RT2hi, RT3lo, RT3hi, RT4lo, RT4hi, RWlo);
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stm RWhi!, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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read_be64_unaligned_4(r1, 4 * 8, RT1lo, RT1hi, RT2lo, RT2hi, RT3lo, RT3hi, RT4lo, RT4hi, RWlo);
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stm RWhi!, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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read_be64_unaligned_4(r1, 8 * 8, RT1lo, RT1hi, RT2lo, RT2hi, RT3lo, RT3hi, RT4lo, RT4hi, RWlo);
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stm RWhi!, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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read_be64_unaligned_4(r1, 12 * 8, RT1lo, RT1hi, RT2lo, RT2hi, RT3lo, RT3hi, RT4lo, RT4hi, RWlo);
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b 2f;
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1:
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/* aligned load */
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add RWhi, sp, #(w(0));
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read_be64_aligned_4(r1, 0 * 8, RT1lo, RT1hi, RT2lo, RT2hi, RT3lo, RT3hi, RT4lo, RT4hi, RWlo);
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stm RWhi!, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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read_be64_aligned_4(r1, 4 * 8, RT1lo, RT1hi, RT2lo, RT2hi, RT3lo, RT3hi, RT4lo, RT4hi, RWlo);
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stm RWhi!, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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read_be64_aligned_4(r1, 8 * 8, RT1lo, RT1hi, RT2lo, RT2hi, RT3lo, RT3hi, RT4lo, RT4hi, RWlo);
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stm RWhi!, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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read_be64_aligned_4(r1, 12 * 8, RT1lo, RT1hi, RT2lo, RT2hi, RT3lo, RT3hi, RT4lo, RT4hi, RWlo);
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2:
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add r1, #(16 * 8);
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stm RWhi, {RT1lo,RT1hi,RT2lo,RT2hi,RT3lo,RT3hi,RT4lo,RT4hi}
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str r1, [sp, #(data)];
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/* preload E & A */
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ldr RElo, [sp, #(_e)];
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ldr REhi, [sp, #(_e) + 4];
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mov RWlo, #0;
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ldr RT2lo, [sp, #(_a)];
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mov RRND, #(80-16);
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ldr RT2hi, [sp, #(_a) + 4];
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mov RWhi, #0;
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.Loop_rounds:
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R(_a, _b, _c, _d, _e, _f, _g, _h, W_0_63, 16);
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R(_h, _a, _b, _c, _d, _e, _f, _g, W_0_63, 17);
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R(_g, _h, _a, _b, _c, _d, _e, _f, W_0_63, 18);
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R(_f, _g, _h, _a, _b, _c, _d, _e, W_0_63, 19);
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R(_e, _f, _g, _h, _a, _b, _c, _d, W_0_63, 20);
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R(_d, _e, _f, _g, _h, _a, _b, _c, W_0_63, 21);
|
|
R(_c, _d, _e, _f, _g, _h, _a, _b, W_0_63, 22);
|
|
R(_b, _c, _d, _e, _f, _g, _h, _a, W_0_63, 23);
|
|
R(_a, _b, _c, _d, _e, _f, _g, _h, W_0_63, 24);
|
|
R(_h, _a, _b, _c, _d, _e, _f, _g, W_0_63, 25);
|
|
R(_g, _h, _a, _b, _c, _d, _e, _f, W_0_63, 26);
|
|
R(_f, _g, _h, _a, _b, _c, _d, _e, W_0_63, 27);
|
|
R(_e, _f, _g, _h, _a, _b, _c, _d, W_0_63, 28);
|
|
R(_d, _e, _f, _g, _h, _a, _b, _c, W_0_63, 29);
|
|
R(_c, _d, _e, _f, _g, _h, _a, _b, W_0_63, 30);
|
|
R(_b, _c, _d, _e, _f, _g, _h, _a, W_0_63, 31);
|
|
|
|
subs RRND, #16;
|
|
bne .Loop_rounds;
|
|
|
|
R(_a, _b, _c, _d, _e, _f, _g, _h, W_64_79, 16);
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|
R(_h, _a, _b, _c, _d, _e, _f, _g, W_64_79, 17);
|
|
R(_g, _h, _a, _b, _c, _d, _e, _f, W_64_79, 18);
|
|
R(_f, _g, _h, _a, _b, _c, _d, _e, W_64_79, 19);
|
|
R(_e, _f, _g, _h, _a, _b, _c, _d, W_64_79, 20);
|
|
R(_d, _e, _f, _g, _h, _a, _b, _c, W_64_79, 21);
|
|
R(_c, _d, _e, _f, _g, _h, _a, _b, W_64_79, 22);
|
|
R(_b, _c, _d, _e, _f, _g, _h, _a, W_64_79, 23);
|
|
R(_a, _b, _c, _d, _e, _f, _g, _h, W_64_79, 24);
|
|
R(_h, _a, _b, _c, _d, _e, _f, _g, W_64_79, 25);
|
|
R(_g, _h, _a, _b, _c, _d, _e, _f, W_64_79, 26);
|
|
R(_f, _g, _h, _a, _b, _c, _d, _e, W_64_79, 27);
|
|
R(_e, _f, _g, _h, _a, _b, _c, _d, W_64_79, 28);
|
|
R(_d, _e, _f, _g, _h, _a, _b, _c, W_64_79, 29);
|
|
R(_c, _d, _e, _f, _g, _h, _a, _b, W_64_79, 30);
|
|
R(_b, _c, _d, _e, _f, _g, _h, _a, W_64_79, 31);
|
|
|
|
ldr r0, [sp, #(ctx)];
|
|
adds RT2lo, RWlo; /* _h = t2 + Maj(_a,_b,_c) */
|
|
ldr r1, [sp, #(data)];
|
|
adc RT2hi, RWhi;
|
|
|
|
ldm r0, {RT1lo,RT1hi,RWlo,RWhi,RT3lo,RT3hi,RT4lo,RT4hi}
|
|
adds RT1lo, RT2lo;
|
|
ldr RT2lo, [sp, #(_b + 0)];
|
|
adc RT1hi, RT2hi;
|
|
ldr RT2hi, [sp, #(_b + 4)];
|
|
adds RWlo, RT2lo;
|
|
ldr RT2lo, [sp, #(_c + 0)];
|
|
adc RWhi, RT2hi;
|
|
ldr RT2hi, [sp, #(_c + 4)];
|
|
adds RT3lo, RT2lo;
|
|
ldr RT2lo, [sp, #(_d + 0)];
|
|
adc RT3hi, RT2hi;
|
|
ldr RT2hi, [sp, #(_d + 4)];
|
|
adds RT4lo, RT2lo;
|
|
ldr RT2lo, [sp, #(_e + 0)];
|
|
adc RT4hi, RT2hi;
|
|
stm r0!, {RT1lo,RT1hi,RWlo,RWhi,RT3lo,RT3hi,RT4lo,RT4hi}
|
|
|
|
ldr RT2hi, [sp, #(_e + 4)];
|
|
ldm r0, {RT1lo,RT1hi,RWlo,RWhi,RT3lo,RT3hi,RT4lo,RT4hi}
|
|
adds RT1lo, RT2lo;
|
|
ldr RT2lo, [sp, #(_f + 0)];
|
|
adc RT1hi, RT2hi;
|
|
ldr RT2hi, [sp, #(_f + 4)];
|
|
adds RWlo, RT2lo;
|
|
ldr RT2lo, [sp, #(_g + 0)];
|
|
adc RWhi, RT2hi;
|
|
ldr RT2hi, [sp, #(_g + 4)];
|
|
adds RT3lo, RT2lo;
|
|
ldr RT2lo, [sp, #(_h + 0)];
|
|
adc RT3hi, RT2hi;
|
|
ldr RT2hi, [sp, #(_h + 4)];
|
|
adds RT4lo, RT2lo;
|
|
adc RT4hi, RT2hi;
|
|
stm r0, {RT1lo,RT1hi,RWlo,RWhi,RT3lo,RT3hi,RT4lo,RT4hi}
|
|
sub r0, r0, #(4 * 8);
|
|
ldr RWlo, [sp, #nblks];
|
|
|
|
sub RK, #(80 * 8);
|
|
subs RWlo, #1;
|
|
bne .Loop_blocks;
|
|
|
|
.Ldone:
|
|
mov r0, #STACK_MAX;
|
|
__out:
|
|
add sp, sp, #STACK_MAX;
|
|
pop {r4-r11, ip, pc};
|
|
.size _gcry_sha512_transform_arm,.-_gcry_sha512_transform_arm;
|
|
|
|
#endif
|
|
#endif
|